RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

A 1/f noise up-conversion reduction technique for voltage-biased RF CMOS oscillators

In this paper, we propose a method to reduce a flicker (1/f) noise upconversion in voltage-biased RF oscillators. Excited by a harmonically rich tank current, a typical oscillation voltage waveform is observed to have asymmetric rise and fall times due to even-order current harmonics flowing into the capacitive part, as it presents the lowest impedance path. The asymmetric oscillation waveform results in an effective impulse sensitivity function of a nonzero dc value, which facilitates the 1/f noise upconversion into the oscillator's 1/f3 phase noise. We demonstrate that if the ω0 tank exhibits an auxiliary resonance at 2ω0, thereby forcing this current harmonic to flow into the equivalent resistance of the 2ω0 resonance, then the oscillation waveform would be symmetric and the flicker noise upconversion would be largely suppressed. The auxiliary resonance is realized at no extra silicon area in both inductor-and transformer-based tanks by exploiting different behaviors of inductors and transformers in differential-and common-mode excitations. These tanks are ultimately employed in designing modified class-D and class-F oscillators in 40 nm CMOS technology. They exhibit an average flicker noise corner of less than 100 kHz.European Research Counci

A 1/f noise upconversion reduction technique applied to class-D and class-F oscillators

2015 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, California, USA, February, 2015The 1/f (flicker) noise upconversion degrades the close-in spectrum of CMOS RF oscillators. The resulting 1/f3 phase noise (PN) can be an issue in PLLs with a loop bandwidth of <;1MHz, which practically implies all cellular phones. A previously published noise-filtering technique [1] and adding resistors in series with gm-device drains [2] have shown significant reduction of the 1/f3 oscillator PN corner. However, the former needs an additional tunable inductor and the latter degrades PN in the 20dB/dec region.European Research CouncilRF Dept. of HiSilico

A 0.5V 0.5mW switching current source oscillator

2015 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Phoenix, Arizona, USA, 17 - 19 May 2015This paper proposes a new RF oscillator topology that is suitable for ultra-low voltage and power applications. By employing alternating current source transistors, the structure combines the benefits of low supply voltage operation of conventional NMOS cross-coupled oscillators together with high current efficiency of the complementary push-pull oscillators. In addition, the 1/f noise upconversion is also reduced. The 40nm CMOS prototype exhibits an average FoM of 189.5 dBc/Hz over 4–5 GHz tuning range, dissipating 0.5mW from 0.5V power supply, while abiding by the technology manufacturing rules.European Research Counci

A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise

We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH ΔΣ time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range digitally-controlled oscillator (DCO). Fabricated in 40nm CMOS, the ADPLL consumes 10.7 mW while outputting 1.73 to 3.38 GHz (after a ÷2 division) and achieves better than -109 dBc/Hz in-band phase noise and 420fsrms integrated jitter

Recent Advances in Theoretical Development of Thermal Atomic Layer Deposition: A Review

Atomic layer deposition (ALD) is a vapor-phase deposition technique that has attracted increasing attention from both experimentalists and theoreticians in the last few decades. ALD is well-known to produce conformal, uniform, and pinhole-free thin films across the surface of substrates. Due to these advantages, ALD has found many engineering and biomedical applications. However, drawbacks of ALD should be considered. For example, the reaction mechanisms cannot be thoroughly understood through experiments. Moreover, ALD conditions such as materials, pulse and purge durations, and temperature should be optimized for every experiment. It is practically impossible to perform many experiments to find materials and deposition conditions that achieve a thin film with desired applications. Additionally, only existing materials can be tested experimentally, which are often expensive and hazardous, and their use should be minimized. To overcome ALD limitations, theoretical methods are beneficial and essential complements to experimental data. Recently, theoretical approaches have been reported to model, predict, and optimize different ALD aspects, such as materials, mechanisms, and deposition characteristics. Those methods can be validated using a different theoretical approach or a few knowledge-based experiments. This review focuses on recent computational advances in thermal ALD and discusses how theoretical methods can make experiments more efficient

Cryo-CMOS Circuits and Systems for Quantum Computing Applications

A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F2,3 digitally controlled oscillator required to manipulate the state of qubits

15.5 Cryo-CMOS circuits and systems for scalable quantum computing

Quantum computing holds the promise to achieve unprecedented computation power and to solve problems today intractable. State-of-the-art quantum processors consist of arrays of quantum bits (qubits) operating at a very low base temperature, typically a few tens of mK, as shown in Fig. 15.5.1 The qubit states degrade naturally after a certain time, upon loss of quantum coherence. For proper operation, an error-correcting loop must be implemented by a classical controller, which, in addition of handling execution of a quantum algorithm, reads the qubit state and performs the required corrections. However, while few qubits (~10) in today's quantum processors can be easily connected to a room-temperature controller, it appears extremely challenging, if not impossible, to manage the thousands of qubits required in practical quantum algorithms [1]